In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
CVE-2024-42279
CVSS base score
7.8 (v3.1)
Severity
HIGH
Attack vector
Local
Last modified
October 30, 2026
CVSS vector
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H
Affected products
linux linux kernel
References
- git.kernel.org Patch
- git.kernel.org Patch
- git.kernel.org
- git.kernel.org Patch